The present invention relates to systems for modeling computer program execution. Specifically, a system is described which will permit simulating parallel execution of parallel hardware and software by modeling the process using sequentially executed code.
In evaluating the performance of computer programs, specifically those for parallel processing systems, it is desirable to model the computer hardware in order to monitor its performance while executing a program. The model is needed as a tool to understand the performance of the program when being executed by a specific processor architecture. By modeling the computer architecture the execution bottlenecks may be identified and analyzed. Once these problems are analyzed, changes in program code may be implemented to improve the overall program efficiency. The real time performance for executing the program may be measured using the model. The use of such simulation techniques also permits measuring hardware performance, permitting changes to the hardware to be monitored as a result of running the program on a model simulating actual hardware performance.
The simulation of computer hardware using sequential logic configured by sequentially executed computer code is made difficult because of data dependencies. The combinational logic which prefetches, decodes and executes the program instructions is order dependent, requiring that data be processed in a certain order.
The order dependency of sequential combinational logic lengthens the time required to simulate program execution. The time for simulation is a function of n.sup.2, where n is the number of logic devices of the combinational logic unit. The length of simulation time necessarily reduces the effectiveness of the computer hardware modeling.